Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

Abstract

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 /spl mu/m CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 /spl mu/m active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 /spl mu/m CMOS technologies (VDS/spl les/5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 /spl mu/m dimensions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>