Leakage Current Reduction

Leakage Current Reduction is a methodological approach in integrated circuit device design that minimizes unintended subthreshold and gate leakage currents through structural, material, or operational optimizations, distinguishing it from other scaling-enhancement techniques by specifically targeting parasitic current pathways in nanoscale transistors.

2.2K

Publications

89.4K

Citations

9.2K

Authors

1.1K

Institutions

Publications per year

2017–2026

491

Authors

9.2K

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    46 publications · 5.4K citations

    27

    h-index

  2. MJ
    M. Jagadesh Kumar

    Indian Institute of Technology Delhi, India

    24 publications · 1.3K citations

    20

    h-index

  3. SB
    Shekhar Borkar

    Intel (United States), United States

    19 publications · 1.8K citations

    17

    h-index

  4. VK
    Volkan Kursun

    University of Wisconsin–Madison, United States

    15 publications · 839 citations

    14

    h-index

  5. VK
    Vijay Kumar Sharma

    Shri Mata Vaishno Devi University, India

    13 publications · 454 citations

    13

    h-index

1–5 of 9.2K

Venues

  1. IEEE Transactions on Electron Devices

    222 publications · 10.6K citations

    52

    h-index

  2. IEEE Electron Device Letters

    183 publications · 9.1K citations

    52

    h-index

  3. Applied Physics Letters

    94 publications · 4.9K citations

    38

    h-index

  4. IEEE Journal of Solid-State Circuits

    45 publications · 2.9K citations

    30

    h-index

  5. 24

    h-index

1–5