Gated-V_dd

TLDR

Deep‑submicron CMOS designs cause significant leakage energy dissipation in microprocessors, largely due to SRAM cells in on‑chip caches whose active usage varies widely across applications. This paper explores an integrated architectural and circuit‑level approach to reducing leakage energy dissipation in instruction caches. We propose gated‑Vdd, a circuit‑level technique that gates the supply voltage to reduce leakage in unused SRAM cells. Our results indicate that gated‑Vdd together with a novel resizable cache architecture reduces energy‑delay by 62% with minimal impact on performance.

Abstract

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appli?cations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruc?tion caches. We propose, gated-Vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-Vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.