Se-Hyun Yang - Concepedia

Author

Se-Hyun Yang

Purdue University West Lafayette

Also Known As

SE-HYUN YANG, Se-Hyun Yang

Publications

1.4K

Citations

H-Index

Concepts

All Affiliations

Purdue University West Lafayette Carnegie Mellon University

About

Se-Hyun Yang is an author at Purdue University West Lafayette specializing in computer architecture, computer engineering, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	1.3K
2	Computer Engineering	8	8	1.3K
3	Computer Science	7	7	652
4	Electrical Engineering	7	7	1.2K
5	Data Science	1	1	103

Se-Hyun Yang

Publications

1.3K

Citations

H-Index

Page 1

	Year	Citations
Gated-V<sub>dd</sub> Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Hardware SecurityElectrical EngineeringDeep-submicron Cmos DesignsEngineeringVlsi Design	2000	666
Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories Michael D. Powell, Se-Hyun Yang, Babak Falsafi, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) Non-volatile MemoryEngineeringVlsi DesignInstruction CachesComputer Architecture	2000	267
Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay Se-Hyun Yang, Michael D. Powell, Babak Falsafi, EngineeringEnergy EfficiencyComputer ArchitectureHigh-performance ArchitectureResizable Cache Design	2004	137
Accurate and Complexity-Effective Spatial Pattern Prediction C.F. Chen, Se-Hyun Yang, Babak Falsafi, EngineeringComputer ArchitectureHardware SecurityData SciencePattern Recognition	2005	103
Reducing leakage in a high-performance deep-submicron instruction cache Michael D. Powell, Se-Hyun Yang, Babak Falsafi, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware SecurityElectrical EngineeringEngineeringVlsi DesignInstruction Caches	2001	96
Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories Michael D. Powell, Se-Hyun Yang, Babak Falsafi, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) Non-volatile MemoryEngineeringVlsi DesignInstruction CachesComputer Architecture	2002	21
A 32nm high-k metal gate application processor with GHz multi-core CPU Se-Hyun Yang, Lee Seogjun, Jae‐Young Lee, EngineeringVlsi DesignComputer ArchitectureEmbedded SystemsProcessor Architecture	2012	18
Near-optimal precharging in high-performance nanoscale CMOS caches Se-Hyun Yang, Babak Falsafi International Symposium on Microarchitecture EngineeringVlsi DesignComputer ArchitectureMulti-channel Memory ArchitectureNanoelectronics	2003	10

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