J. Kedzierski

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

Chenming Hu, Jeffrey Bokor, Tsu‐Jae King et al. · IEEE Transactions on Electron Devices · 2000 · 1.6K citations

Low-power Electronics, Electrical Engineering, Gate Length +9

Silicon Device Scaling to the Sub-10-nm Regime

M. Ieong, B. Doris, J. Kedzierski et al. · Science · 2004 · 564 citations

Device Speed, Electrical Engineering, Silicon Device Scaling +13

Epitaxial Graphene Transistors on SiC Substrates

J. Kedzierski, Pei-Lan Hsu, Paul Healey et al. · IEEE Transactions on Electron Devices · 2008 · 418 citations · Full text

Semiconductors, Graphene Nanomeshes, Electrical Engineering +14

Sub 50-nm FinFET: PMOS

Xuejue Huang, Wen‐Chin Lee, C. Kuo et al. · 2003 · 365 citations

Low-power Electronics, Electrical Engineering, Quasi-planar Nature +11

FinFET design considerations based on 3-D simulation and analytical modeling

Guangsheng Pei, J. Kedzierski, Phil Oldiges et al. · IEEE Transactions on Electron Devices · 2002 · 296 citations

Device Modeling, Electrical Engineering, Physical Design (Electronics) +14