Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

TLDR

In deep‑submicrometer CMOS, shrinking threshold voltage, channel length, and gate oxide thickness cause leakage current to dominate power dissipation, making accurate identification and modeling of leakage components essential for low‑power design. The paper reviews intrinsic transistor leakage mechanisms and investigates circuit techniques to reduce leakage power. The review covers intrinsic leakage mechanisms and discusses channel‑engineering methods such as retrograde wells and halo doping, as well as circuit techniques for leakage reduction.

Abstract

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.