Electromigration performance of Cu pillar bump for flip chip packaging with bump on trace by using thermal compression bonding

Abstract

In this study, electromigration (EM) performance of 60μm pitch Cu pillar bumps assembled with bump on trace (BOT) process by using thermal compression bonding with non-conductive paste (TCNCP) is investigated. Emphasis is placed on the EM experimental measurement and analysis of the Cu pillar bump on trace. The test temperature ranges from 140–160°C and the current of 500–900mA are applied, which corresponding to the current density of 50–90kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The substrate finish is organic solderability preservative (OSP) on the Cu trace. The Cu pillar height is 45μm including 28μm Cu post + 2μm Ni + 15μm lead free SnAg solder cap. The bump size is 30 × 40μm (elongated). The experiment result shows the joint solder is transferred to intermetallic compound (IMC) soon after EM test due to small solder joint height (7∼8 um) after bonding. The EM performance of Sn-Cu IMC bumps outperform standard lead-free solder bump. The electromigration life with 4X tightened failure criteria of the Cu pillar bumped SnAg solder joints on trace is 3X better than that of the conventional lead-free SnAg or SnCu solder joints. The EM failures of Cu pillar bumped on trace are caused by void and crack due to solder creeping Cu post side wall. It shows the thermal driven failure is the dominant factor and the defects will be enhanced or reduced based on the electron flow direction. It's different to the conventional lead free solder-joint failure mode with serious cracks between the bulk solder and the (Cu, Ni) <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</inf> Sn <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</inf> intermetallic compound.