Physical origins of plasma damage and its process/gate area effects on high-k metal gate technology

Abstract

In advanced high-k metal gate (HK/MG) technologies, plasma induced damage (PID) during process is unavoidable and has the potential to degrade device performance and gate dielectrics. In most cases, PID can be simply managed by process optimization but the root cause and relevant solutions remain unclear. In this study, (i) the origin of plasma damage on Hafnium-based gate oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) devices is verified as bulk traps, located near the HK/oxide interface with negligible latent damage. To resolve this PID issue, we (ii) justify that it can be significantly diminished by optimized post gate etching plasma and improved gate oxide robustness. Moreover, (iii) a quantitative PID model, for the first time, is successfully demonstrated for the incorporated gate area effect by Ig tail of ~4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device area, which reduces admissible antenna area for large gate areas in design rule. Gate area scaling is also validated to be crucial for plasma charging damage.