A. Amerasekera

The impact of technology scaling on ESD robustness and protection circuit design

A. Amerasekera, C. Duvvury · IEEE Transactions on Components Packaging and Manufacturing Technology Part A · 1995 · 158 citations

Hardware Security, Electrical Engineering, Engineering +9

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

A. Amerasekera, S. Ramaswamy, Mi-Chang Chang et al. · 1996 · 147 citations

Engineering, Vlsi Design, Circuit-level Simulator +16

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Mike Harwood, N. Warke, R. S. Simpson et al. · 2007 · 145 citations

Electrical Engineering, Engineering, Digital Receiver Equalization +11

ESD: a pervasive reliability concern for IC technologies

C. Duvvury, A. Amerasekera · Proceedings of the IEEE · 1993 · 144 citations

Engineering, Electronic Design, Computer Architecture +17

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

A. Amerasekera, L. van Roozendaal, J. J. P. Bruines et al. · IEEE Transactions on Electron Devices · 1991 · 114 citations

Engineering, Esd-related Process, Design Parameters +17