C. Duvvury - Concepedia

Author

C. Duvvury

Texas Instruments (United States)

Also Known As

C Duvvury, C. Duvvury, Charvaka Duvvury, Gianluca Boselli Charvaka Duvvury

Publications

2.4K

Citations

H-Index

Concepts

All Affiliations

Texas Instruments (United States)University of Illinois Urbana-Champaign Stanford SystemX Alliance Integrated Systems Solutions (United States)Stanford University

About

C. Duvvury is an author at Texas Instruments (United States) specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	27	54	2.2K
2	Applied Physics	14	19	630
3	Natural Sciences	2	2	89
4	Chemistry	2	2	89
5	Education	1	1	10

C. Duvvury

Publications

2.2K

Citations

H-Index

Page 1

	Year	Citations
The impact of technology scaling on ESD robustness and protection circuit design A. Amerasekera, C. Duvvury IEEE Transactions on Components Packaging and Manufacturing Technology Part A Hardware SecurityElectrical EngineeringEngineeringVlsi DesignCircuit Design	1995	158
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations A. Amerasekera, S. Ramaswamy, Mi-Chang Chang, EngineeringVlsi DesignCircuit-level SimulatorPower ElectronicsPhysical Design (Electronics)	1996	147
ESD: a pervasive reliability concern for IC technologies C. Duvvury, A. Amerasekera Proceedings of the IEEE EngineeringElectronic DesignComputer ArchitectureIntegrated CircuitsHardware Systems	1993	144
Dynamic gate coupling of NMOS for efficient output ESD protection C. Duvvury, C.H. Diaz Hardware SecurityDevice ModelingElectrical EngineeringEngineeringDynamic Gate Coupling	1992	131
Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes A. Amerasekera, C. Duvvury, V. Reddy, Salicide EffectsElectrical EngineeringLocal Substrate PotentialEngineeringVlsi Design	2002	91
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices C.H. Diaz, Sung-Mo Kang, C. Duvvury IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringPower Electronic SystemsPower ElectronicsReliability EngineeringHigh Voltage Engineering	1994	85
Substrate pump NMOS for ESD protection applications C. Duvvury, S. Ramaswamy, A. Amerasekera, Hardware SecurityElectrical EngineeringDevice Design OptimizationVlsi DesignUniform Npn Protection	2002	80
Temperature-Dependent Electrical Resistivity of Potassium below 2 K J. A. Rowlands, C. Duvvury, S. B. Woods Physical Review Letters EngineeringChemistryElectronic StructureElectron PhysicResistor	1978	75
Internal chip ESD phenomena beyond the protection circuit C. Duvvury, R.N. Rountree, Oliver Adams IEEE Transactions on Electron Devices Hardware TrojanElectrical EngineeringEngineeringInput/output Electrostatic DischargeHigh Voltage Engineering	1988	75
Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes Jie Chen, E. A. Amerasekera, C. Duvvury IEEE Transactions on Electron Devices Hardware SecurityNmos Esd ProtectionElectrical EngineeringEngineeringVlsi Design	1998	68

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