Harold Philipsen - Concepedia

Author

Harold Philipsen

Also Known As

H. G. G. Philipsen, H. Philipsen, H.G.G. Philipsen, Harold G. G. Philipsen, Harold G. Philipsen, Harold G.G. Philipsen, Harold Philipsen, Philipsen, H., Prajapati, V., Z Harold Philipsen

Publications

1.1K

Citations

H-Index

Concepts

All Affiliations

IMEC KU Leuven Imec the Netherlands Utrecht University Kansai University

About

Harold Philipsen is an author at IMEC specializing in engineering, materials science, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	18	29	909
2	Applied Physics	15	21	619
3	Chemical Engineering	5	5	132
4	Chemistry	5	5	109
5	Education	1	1	14

Harold Philipsen

Publications

948

Citations

H-Index

Page 1

	Year	Citations
Copper plating for 3D interconnects Aleksandar Radisic, Ole Lühn, Harold Philipsen, Microelectronic Engineering Materials ScienceMaterials Engineering3D Ic ArchitectureEngineeringFabrication Technique	2010	82
Impact of post-plating anneal and through-silicon via dimensions on Cu pumping Joke De Messemaeker, Olalla Varela Pedreira, Bart Vandevelde, EngineeringSilicon On InsulatorInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)	2013	61
Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias Fumihiro Inoue, Harold Philipsen, Aleksandar Radisic, Electrochimica Acta Materials ScienceEpitaxial GrowthEngineeringNanoelectronicsSurface Science	2013	56
Anisotropy in the wet-etching of semiconductors John J. Kelly, Harold Philipsen Current Opinion in Solid State and Materials Science SemiconductorsEngineeringPhysicsSurface ScienceApplied Physics	2005	53
Implementation of an industry compliant, 5&#x00D7;50&#x03BC;m, via-middle TSV technology on 300mm wafers A. Redolfi, Dimitrios Velenis, Sarasvathi Thangaraju, EngineeringSilicon ViasIntegrated CircuitsInterconnect (Integrated Circuits)Cmos Flow	2011	52
Correlation between Cu microstructure and TSV Cu pumping Joke De Messemaeker, Olalla Varela Pedreira, Harold Philipsen, EngineeringGrain SizeCu MicrostructureInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)	2014	50
3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias Yann Civale, Deniz Sabuncuoglu Tezcan, Harold Philipsen, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringIntegrated CircuitsTemporary CarriersWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2011	50
Large Area Copper Plated Silicon Solar Cell Exceeding 19.5% Efficiency Loïc Tous, Richard Russell, J. Das, Energy Procedia Materials ScienceElectrical EngineeringEngineeringEnergy EfficiencyHomogeneous Emitter	2012	48
Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging Deniz Sabuncuoglu Tezcan, Fabrice Duval, Harold Philipsen, EngineeringWafer Scale ProcessingAdvanced Packaging (Semiconductors)Printed ElectronicsElectronic Packaging	2009	48
A Simple Copper Metallisation Process for High Cell Efficiencies and Reliable Modules Richard Russell, Loïc Tous, Harold Philipsen, EU PVSEC	2012	39

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