Fabrice Duval

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

Yann Civale, Deniz Sabuncuoglu Tezcan, Harold Philipsen et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 50 citations

Engineering, Electrical Engineering, Materials Science +14

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

Deniz Sabuncuoglu Tezcan, Fabrice Duval, Harold Philipsen et al. · 2009 · 48 citations

Engineering, Electrical Engineering, Materials Science +16

Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications

Fabrice Duval, Chukwudi Okoro, Yann Civale et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 33 citations

Engineering, Materials Engineering, Materials Science +17

A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch

Arnita Podpod, John Slabbekoorn, Alain Phommahaxay et al. · 2018 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +17

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

Yann Civale, Deniz Sabuncuoglu Tezcan, Harold Philipsen et al. · 2009 · 27 citations

Engineering, Electrical Engineering, Materials Science +17