3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

Abstract

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ø</sup> TSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.