Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

Abstract

A scalable generic through silicon via (TSV) process is developed using spin-on dielectric polymer as isolation layer where deep annular trenches in silicon are filled with the polymer. Following parameters are found to be affecting the polymer material spreading on the wafer surface and the filling performance: pre-treatments on the wafer surface, TSV density and physical properties of the polymer. Yielding TSV chains are measured on the fabricated wafers and the TSV resistance is found to be <100 mOmega. It is a via-last TSV process which is applicable to any silicon technology.