3-D TCAD simulation study of the single event effect on 25 nm raised source-drain FinFET

Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells

Kenneth P. Rodbell, David F. Heidel, Henry H. K. Tang et al. · IEEE Transactions on Nuclear Science · 2007 · 186 citations

Natural Sciences, Electrical Engineering, Physics +14

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Hikaru Kawasaki, V. Basker, T. Yamashita et al. · 2009 · 94 citations

Engineering, Computer Engineering, Electrical Engineering +17

Impacts of front-end and middle-end process modifications on terrestrial soft error rate

P. Roche, Gilles Gasiot · IEEE Transactions on Device and Materials Reliability · 2005 · 91 citations

Engineering, Computer Engineering, Electrical Engineering +17

Hierarchical approach to "atomistic" 3-D MOSFET simulation

Asen Asenov, A. R. Brown, J. H. Davies et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999 · 72 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 25-nm gate-length FinFET transistor module for 32nm node

Chang-Yun Chang, Tsung-Lin Lee, C. Wann et al. · 2009 · 62 citations

Engineering, Computer Engineering, Electrical Engineering +17