Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Abstract

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</inf> ) degraded by 3-D structure with thin Si-body. The issue of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> -mismatch is discussed for continuous FinFET SRAM cell-size scaling.