Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Hikaru Kawasaki, V. Basker, T. Yamashita, +30

EngineeringVlsi DesignSidewall Image TransferIntegrated CircuitsInterconnect (Integrated Circuits) +16

A 0.063 µm<sup>2</sup> FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

V. Basker, T. Standaert, Hikaru Kawasaki, +37

Novel Integration SchemeEngineeringVlsi DesignMicroscopyPattern Transfer +19

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

Isaac Lauer, N. Loubet, S.D. Kim, +9

EngineeringFinfet TechnologySilicon On InsulatorSemiconductor DeviceMinimal Deviation +16

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Takashi Yamashita, V. Basker, T. Standaert, +41

Symposium on VLSI Technology

Electrical EngineeringAdvanced Fin FormationEngineeringVlsi DesignSelf-heating Correction +10

22 nm technology compatible fully functional 0.1 μm<sup>2</sup> 6T-SRAM cell

Bala S. Haran, A. Kumar, Lahir Shaik Adam, +44

Functional 0.1Nm TechnologyElectrical EngineeringEngineeringVlsi Design +9

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

Kangguo Cheng, A. Khakifirooz, P. Kulkarni, +28

Symposium on VLSI Technology

Electrical EngineeringNovel Integration SchemeEngineeringNew Integration SchemeEtsoi Devices +13

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

A. Paul, A. Bryant, Terence B. Hook, +15

Sub XmlnsEngineeringIntegrated CircuitsMulti-fin Soi FinfetsSilicon On Insulator +14

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

A. Khakifirooz, Kangguo Cheng, P. Kulkarni, +36

EngineeringVlsi DesignSilicon On InsulatorInterconnect (Integrated Circuits)Future Low Power +15

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

K. Maitra, A. Khakifirooz, Pranita Kulkarni, +15

IEEE Electron Device Letters

SemiconductorsHigh-performance Logic ApplicationsElectrical EngineeringElectronic DevicesEngineering +13

Superior PBTI Reliability for SOI FinFET Technologies and Its Physical Understanding

Miaomiao Wang, Ramachandran Muralidhar, J. H. Stathis, +3

IEEE Electron Device Letters

Soi Finfet TechnologiesEngineeringPhysical UnderstandingSemiconductor DeviceAdvanced Packaging (Semiconductors) +16