T. Yamashita

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Hikaru Kawasaki, V. Basker, T. Yamashita et al. · 2009 · 94 citations

Engineering, Vlsi Design, Sidewall Image Transfer +18

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Vlsi Design +15

Study of Gettering Mechanisms in Silicon: Competitive Gettering between Phosphorus Diffusion Gettering and Other Gettering Sites

Mohammad Bagher Shabani, T. Yamashita, Etsuoru Morita · Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena · 2007 · 48 citations

Engineering, Silicon On Insulator, Phosphorus Diffusion Gettering +16

A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

Y. Komatsu, Yutaka Arima, Tadahiro Fujimoto et al. · 2004 · 32 citations

Hardware Security, Low-power Electronics, Electrical Engineering +13

Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS

T. Miyake, T. Yamashita, N. Asari et al. · 2002 · 20 citations

Low-power Electronics, Electrical Engineering, Engineering +13