A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

Abstract

In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using /spl alpha/-particles, and 1-order higher immunity through neutron irradiation.