K. Ishibashi

Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics

Masahiko Miyamoto, Hiroyuki Ohta, Yuho Kumagai et al. · IEEE Transactions on Electron Devices · 2004 · 88 citations

Materials Engineering, Electrical Engineering, Mosfet Parametric Characteristics +15

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

Hiroyuki Mizuno, K. Ishibashi, T. Shimura et al. · IEEE Journal of Solid-State Circuits · 1999 · 84 citations

Low-power Electronics, Non-volatile Memory, Electrical Engineering +12

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

Masanao Yamaoka, Kensuke Osada, K. Ishibashi · IEEE Journal of Solid-State Circuits · 2004 · 68 citations

Low-power Electronics, Dba Scheme, Electrical Engineering +12

A 1-V TFT-load SRAM using a two-step word-voltage method

K. Ishibashi, K. Takasugi, T. Hashimoto et al. · IEEE Journal of Solid-State Circuits · 1992 · 39 citations

Low-power Electronics, Electrical Engineering, Engineering +8

A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

Y. Komatsu, Yutaka Arima, Tadahiro Fujimoto et al. · 2004 · 32 citations

Hardware Security, Low-power Electronics, Electrical Engineering +13