A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, +3

IEEE Journal of Solid-State Circuits

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control

Ryuta Tsuchiya, M. Horiuchi, S. Kimura, +6

Low-power ElectronicsNon-volatile MemoryElectrical EngineeringIon ImplantationUltra-thin Box +11

Low-power embedded SRAM modules with expanded margins for writing

Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, +5

Hardware SecurityLow-power ElectronicsElectrical EngineeringMargin ExpansionEngineering +10

Low-Power Embedded SRAM Modules with Expanded Margins for Writing

Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, +5

IEICE Technical Report; IEICE Tech. Rep.

Hardware SecurityLow-power ElectronicsElectrical EngineeringMargin ExpansionEngineering +10

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing

Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, +3

EngineeringComputer Architecture20K-spin Ising ChipQuantum ComputingCombinational Optimization Problem +14

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions

Kasho Yamamoto, Kazushi Kawamura, Kota Ando, +7

IEEE Journal of Solid-State Circuits

Previous AnnealersEngineeringComputer ArchitectureStatica Prototype ChipMulti-channel Memory Architecture +17

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, +5

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringVlsi DesignComputer ArchitectureMulti-channel Memory Architecture +14

Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

Masanao Yamaoka, Kensuke Osada, Ryuta Tsuchiya, +3

Low-power ElectronicsNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design +11

90-nm Process-Variation Adaptive Embedded SRAM Modules With Power-Line-Floating Write Technique

Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, +5

IEEE Journal of Solid-State Circuits

Low-power ElectronicsNon-volatile MemoryElectrical EngineeringPower-aware ComputingEngineering +11

Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM

Naoki Tega, Hiroshi Miki, Masanao Yamaoka, +6

EngineeringVlsi DesignCapture Cross SectionSram MarginScaled-down Sram +14