A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

TLDR

Solving combinatorial optimization problems will be essential for enabling the IoT era. The authors propose a new Ising computing architecture implemented with CMOS circuits. The architecture maps problems to an Ising model, uses CMOS annealing to find solutions, and is implemented on a 20,000‑spin prototype fabricated in a 65‑nm process. The prototype operates at 100 MHz, confirms its ability to solve combinatorial optimization problems, and achieves a power efficiency roughly 1,800 times greater than a general‑purpose CPU running an approximation algorithm.

Abstract

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, "CMOS annealing" is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.