Chihiro Yoshimura

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi et al. · IEEE Journal of Solid-State Circuits · 2015 · 358 citations

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing

Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi et al. · 2015 · 110 citations

Engineering, Computer Architecture, 20K-spin Ising Chip +16

2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura et al. · 2019 · 71 citations

Engineering, Vlsi Design, Computer Architecture +16

A 2 $\times$ 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura et al. · IEEE Journal of Solid-State Circuits · 2019 · 64 citations

Engineering, Vlsi Design, Emerging Memory Technology +19

4.6 A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems

Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura et al. · 2021 · 61 citations

Engineering, Vlsi Design, Computer Architecture +23