Takashi Takemoto

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions

Kasho Yamamoto, Kazushi Kawamura, Kota Ando et al. · IEEE Journal of Solid-State Circuits · 2020 · 115 citations

Computing, Computer Engineering, Computer Science +13

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

K. Fukuda, Hiroki Yamashita, Goichi Ono et al. · IEEE Journal of Solid-State Circuits · 2010 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17

2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura et al. · 2019 · 73 citations

Engineering, Computer Engineering, Computer Science +13

A 25-to-28 Gb/s High-Sensitivity (<formula formulatype="inline"> <tex Notation="TeX">$-$</tex></formula>9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects

Takashi Takemoto, Hiroki Yamashita, Toru Yazaki et al. · IEEE Journal of Solid-State Circuits · 2014 · 72 citations

Engineering, Computer Engineering, Electrical Engineering +17

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions

Kasho Yamamoto, Kota Ando, Normann Mertig et al. · 2020 · 71 citations

Computing, Computer Engineering, Computer Science +14