Kasho Yamamoto

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions

Kasho Yamamoto, Kazushi Kawamura, Kota Ando et al. · IEEE Journal of Solid-State Circuits · 2020 · 108 citations

Previous Annealers, Engineering, Computer Architecture +19

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions

Kasho Yamamoto, Kota Ando, Normann Mertig et al. · 2020 · 66 citations

Artificial Intelligence, Combinatorial Optimization Problems, Engineering +20

4.6 A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems

Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura et al. · 2021 · 61 citations

Engineering, Vlsi Design, Computer Architecture +23

A Time-Division Multiplexing Ising Machine on FPGAs

Kasho Yamamoto, Wei-Qiang Huang, Shinya Takamaeda-Yamazaki et al. · 2017 · 23 citations

Ising Machine, Conventional Annealing Machine, Engineering +15

A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems

Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura et al. · 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) · 2021 · 12 citations