D. Mocuta

The Complementary FET (CFET) for CMOS scaling beyond N3

Julien Ryckaert, P. Schuddinck, Pieter Weckx et al. · 2018 · 229 citations

Engineering, Computer Engineering, Electrical Engineering +17

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

Hans Mertens, R. Ritzenthaler, Andriy Hikavyy et al. · 2016 · 198 citations

Engineering, Electrical Engineering, Materials Science +17

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

Hans Mertens, R. Ritzenthaler, Adrian Chasin et al. · 2016 · 161 citations

Engineering, Electrical Engineering, Materials Science +17

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

Hans Mertens, R. Ritzenthaler, V. Peña et al. · 2017 · 130 citations

Engineering, Electrical Engineering, Microelectronics +16

Impact of Wire Geometry on Interconnect <italic>RC</italic> and Circuit Delay

Ivan Ciofi, Antonino Contino, Philippe Roussel et al. · IEEE Transactions on Electron Devices · 2016 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +17