P. Schuddinck

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

Doyoung Jang, Dmitry Yakimets, Geert Eneman et al. · IEEE Transactions on Electron Devices · 2017 · 275 citations

Device Modeling, Nanowire Transistors, Electrical Engineering +13

The Complementary FET (CFET) for CMOS scaling beyond N3

Julien Ryckaert, P. Schuddinck, Pieter Weckx et al. · 2018 · 206 citations

Finfet Device, Engineering, Vlsi Design +18

Vertical GAAFETs for the Ultimate CMOS Scaling

Dmitry Yakimets, Geert Eneman, P. Schuddinck et al. · IEEE Transactions on Electron Devices · 2015 · 191 citations

Power Consumption, Electrical Engineering, Engineering +13

Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI

Gage Hills, M. Garcia Bardon, G. Doornbos et al. · IEEE Transactions on Nanotechnology · 2018 · 131 citations · Full text

Engineering, Vlsi Design, Energy Efficiency +19

Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

Dmitry Yakimets, M. Garcia Bardon, Doyoung Jang et al. · 2017 · 115 citations

Low-power Electronics, Power Aware Finfet, Electrical Engineering +15