T. Chiarella

3D stacked IC demonstration using a through Silicon Via First approach

J. Van Olmen, A. Mercha, Guruprasad Katti et al. · 2008 · 141 citations

Engineering, Silicon Vias, Oscillator Topologies +18

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha et al. · Solid-State Electronics · 2010 · 120 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

S. Subramanian, M. Reza Hosseini, T. Chiarella et al. · 2020 · 109 citations

Engineering, N14 Platform, Interconnect (Integrated Circuits) +16

Deposition of HfO2 on germanium and the impact of surface pretreatments

Sven Van Elshocht, Bert Brijs, Matty Caymax et al. · Applied Physics Letters · 2004 · 106 citations

Engineering, Chemistry, Chemical Deposition +20

Self-heating on bulk FinFET from 14nm down to 7nm node

Doyoung Jang, E. Bury, R. Ritzenthaler et al. · 2015 · 92 citations

Device Modeling, Scaled Bulk Finfets, Electrical Engineering +14