J. Van Olmen

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Computer Engineering, Electrical Engineering +17

3D stacked IC demonstration using a through Silicon Via First approach

J. Van Olmen, A. Mercha, Guruprasad Katti et al. · 2008 · 141 citations

Engineering, Computer Engineering, Electrical Engineering +17

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

A. Mercha, Geert Van der Plas, Victor Moroz et al. · 2010 · 119 citations

Engineering, Computer Engineering, Electrical Engineering +17

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

Guruprasad Katti, Michele Stucchi, J. Van Olmen et al. · IEEE Electron Device Letters · 2010 · 86 citations

Engineering, Electrical Engineering, Manufacturing Engineering +17

Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

J. Van Olmen, Cedric Huyghebaert, Jan Coenen et al. · Microelectronic Engineering · 2010 · 79 citations

Engineering, Materials Engineering, Materials Science +16