The Complementary FET (CFET) for CMOS scaling beyond N3

TLDR

The CFET device, a stacked n‑type vertical sheet on a p‑type fin, is evaluated within a design‑technology co‑optimization framework. The study aims to reduce the parasitic resistance of deep vias by introducing advanced MOL contacts with thin barriers. The process flow demands precise control of the elevation dimension to ensure manufacturability. TCAD analysis shows the CFET can outperform finFETs and meet N3 power and performance targets, while a double‑level access provides 50 % structural scaling of standard cells and SRAM.

Abstract

The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.