Yasser Sherazi

The Complementary FET (CFET) for CMOS scaling beyond N3

Julien Ryckaert, P. Schuddinck, Pieter Weckx et al. · 2018 · 206 citations

Finfet Device, Engineering, Vlsi Design +18

Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

Dmitry Yakimets, M. Garcia Bardon, Doyoung Jang et al. · 2017 · 115 citations

Low-power Electronics, Power Aware Finfet, Electrical Engineering +15

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

M. Garcia Bardon, Yasser Sherazi, P. Schuddinck et al. · 2016 · 68 citations

Low-power Electronics, Holistic Design-device Co-optimization, Electrical Engineering +15

Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

P. Schuddinck, Odysseas Zografos, Pieter Weckx et al. · 2019 · 66 citations

Engineering, Vlsi Design, Analog Design +19

Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

M. Garcia Bardon, Yasser Sherazi, Doyoung Jang et al. · 2018 · 53 citations

Electrical Engineering, Physical Design (Electronics), Power-performance Trade-offs +14