2017 · 118 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsNanoelectronicsPower OptimizationDevice OptimizationFin Field-effect Transistor ScalingFin Field-effect TransistorsLeakage Current ReductionLow-power Cmos DesignRelative Performance TargetsStandard CellsUltra-low-power Cmos
In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal pitch 21 nm and achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by power and performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 nm width are competitive with FinFETs made with two fins while relaxing the constraints on layout design rules.