Bertrand Parvais

Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective

V. Subramanian, Bertrand Parvais, Jonathan Borremans et al. · IEEE Transactions on Electron Devices · 2006 · 150 citations

Device Modeling, Low-power Electronics, Electrical Engineering +10

3D stacked IC demonstration using a through Silicon Via First approach

J. Van Olmen, A. Mercha, Guruprasad Katti et al. · 2008 · 141 citations

Engineering, Silicon Vias, Oscillator Topologies +18

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha et al. · Solid-State Electronics · 2010 · 120 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

Dmitry Yakimets, M. Garcia Bardon, Doyoung Jang et al. · 2017 · 115 citations

Low-power Electronics, Power Aware Finfet, Electrical Engineering +15

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Arnout Beckers, Farzan Jazaeri, Alexander Grill et al. · IEEE Journal of the Electron Devices Society · 2020 · 103 citations · Full text

Device Modeling, Low-power Electronics, Electrical Engineering +13