Odysseas Zografos

Buried Power Rails and Back-side Power Grids: Arm^® CPU Power Delivery Network Design Beyond 5nm

Divya Prasad, S. S. Teja Nibhanupudi, Shidhartha Das et al. · 2019 · 69 citations

Engineering, Computer Engineering, Electrical Engineering +14

Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

P. Schuddinck, Odysseas Zografos, Pieter Weckx et al. · 2019 · 67 citations

Engineering, Computer Engineering, Electrical Engineering +16

Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS

Odysseas Zografos, Bart Sorée, Adrien Vaysset et al. · 2015 · 55 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

Rongmei Chen, Melina Lofrano, Gioele Mirabelli et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +17

Non-volatile spin wave majority gate at the nanoscale

Odysseas Zografos, Sourav Dutta, Mauricio Manfrini et al. · AIP Advances · 2017 · 37 citations · Full text

Engineering, Electrical Engineering, Magnetic Materials +14