Odysseas Zografos

Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

P. Schuddinck, Odysseas Zografos, Pieter Weckx et al. · 2019 · 66 citations

Engineering, Vlsi Design, Analog Design +19

Buried Power Rails and Back-side Power Grids: Arm^® CPU Power Delivery Network Design Beyond 5nm

Divya Prasad, S. S. Teja Nibhanupudi, Shidhartha Das et al. · 2019 · 63 citations

Engineering, Vlsi Design, Energy Efficiency +18

Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS

Odysseas Zografos, Bart Sorée, Adrien Vaysset et al. · 2015 · 55 citations · Full text

Low-power Electronics, Magnetism, Electrical Engineering +15

Non-volatile spin wave majority gate at the nanoscale

Odysseas Zografos, Sourav Dutta, Mauricio Manfrini et al. · AIP Advances · 2017 · 36 citations · Full text

Spintronics, Magnetism, Electrical Engineering +13

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

Rongmei Chen, Melina Lofrano, Gioele Mirabelli et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 33 citations

A14 Node, Engineering, Energy Efficiency +18