Razor: a low-power pipeline based on circuit-level timing speculation

Dan Ernst, Nam Sung Kim, Shidhartha Das, +8

International Symposium on Microarchitecture

EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitecturePower Aware Computing +14

Razor: a low-power pipeline based on circuit-level timing speculation

Daniel Ernst, Nam Sung Kim, Shidhartha Das, +8

EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitecturePower Aware Computing +14

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

Shidhartha Das, Carlos Tokunaga, Sanjay Pant, +5

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignMeasurementPower Optimization (Eda)Computer Architecture +16

Razor: circuit-level correction of timing errors for low-power operation

Daniel Ernst, Shidhartha Das, Sang Hyun Lee, +5

IEEE Micro

Hardware SecurityVoltage MarginsPower-aware ComputingEngineeringVlsi Design +13

A Self-Tuning DVS Processor Using Delay-Error Detection and Correction

Shidhartha Das, David Roberts, Sang Hyun Lee, +5

IEEE Journal of Solid-State Circuits

Low-power ElectronicsHardware SecurityElectrical EngineeringError DetectionSitu Error Detection +12

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

David Blaauw, S. A. Kalaiselvan, Kevin Lai, +5

EngineeringError Control TechniqueMeasurementElectronic Design AutomationVerification +21

A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

David Bull, Shidhartha Das, Karthik Shivashankar, +3

IEEE Journal of Solid-State Circuits

Low-power ElectronicsPower-efficient 32Electrical EngineeringEngineeringVlsi Design +11

A self-tuning dvs processor using delay-error detection and correction

Shidhartha Das, Sanjay Pant, David Roberts, +5

Low-power ElectronicsHardware SecurityElectrical EngineeringCorrection SchemeVlsi Design +13

Harnessing voltage margins for energy efficiency in multicore CPUs

George N. Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, +3

EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureScaled Voltage Conditions +15

Buried Power Rails and Back-side Power Grids: Arm^® CPU Power Delivery Network Design Beyond 5nm

Divya Prasad, S. S. Teja Nibhanupudi, Shidhartha Das, +12

EngineeringVlsi DesignEnergy EfficiencyPower Optimization (Eda)Back-side Power Delivery +16