A Self-Tuning DVS Processor Using Delay-Error Detection and Correction

TLDR

Traditional DVS techniques require large safety margins to guarantee correctness under worst‑case conditions, reducing energy efficiency. The paper introduces Razor, a DVS technique that uses in‑situ error detection and correction to recover from timing errors. Razor automatically reduces supply voltage to the point of first failure using error detection and correction, and can be scaled below that point to balance energy savings against error‑correction overhead; it was implemented on a 64‑bit processor in 0.18‑µm technology. Silicon measurements on 33 dies show Razor DVS achieves an average 50 % energy savings over worst‑case conditions by targeting a 0.1 % error rate at 120 MHz.

Abstract

In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which incorporates an in situ error detection and correction mechanism to recover from timing errors. We also present the implementation details and silicon measurements results of a 64-bit processor fabricated in 0.18-/spl mu/m technology that uses Razor for supply voltage control. Traditional DVS techniques require significant voltage safety margins to guarantee computational correctness at the worst case combination of process, voltage and temperature conditions, leading to a loss in energy efficiency. In Razor-based DVS, however, the supply voltage is automatically reduced to the point of first failure using the error detection and correction mechanism, thereby eliminating safety margins while still ensuring correct operation. In addition, the supply voltage can be intentionally scaled below the point of first failure of the processor to achieve an optimal tradeoff between energy savings from further voltage reduction and energy overhead from increased error detection and correction activity. We tested and measured savings due to Razor DVS for 33 different dies and obtained an average energy savings of 50% over worst case operating conditions by scaling supply voltage to achieve a 0.1% targeted error rate, at a fixed frequency of 120 MHz.