E. Leobandung - Concepedia

Author

E. Leobandung

IBM (United States)

Also Known As

E. Leobandung, Effendi Leobandung, Leobandung, Effendi

Publications

2.3K

Citations

H-Index

Concepts

All Affiliations

IBM (United States)IBM Research - Thomas J. Watson Research Center University of Minnesota GlobalFoundries (United States)Toshiba (United States)

About

E. Leobandung is an author at IBM (United States) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	24	42	2.1K
2	Applied Physics	21	34	1.8K
3	Computer Engineering	16	17	654
4	Social Sciences	1	1	39
5	Biomedical Engineering	1	1	60

E. Leobandung

Publications

2.2K

Citations

H-Index

Page 1

	Year	Citations
A Silicon Single-Electron Transistor Memory Operating at Room Temperature L. Jay Guo, E. Leobandung, Stephen Y. Chou Science Room TemperatureElectrical EngineeringNon-volatile MemoryEngineeringControl Gate	1997	385
Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperatures over 100 K E. Leobandung, L. Jay Guo, Yun Wang, Applied Physics Letters Quantum ScienceElectrical EngineeringEngineeringQuantum ComputingPhysics	1995	230
A room-temperature silicon single-electron metal–oxide–semiconductor memory with nanoscale floating-gate and ultranarrow channel L. Jay Guo, E. Leobandung, Stephen Y. Chou Applied Physics Letters Non-volatile MemoryEngineeringEmerging Memory TechnologySemiconductor MaterialsSemiconductors	1997	151
Single hole quantum dot transistors in silicon E. Leobandung, L. Jay Guo, Stephen Y. Chou Applied Physics Letters SemiconductorsSemiconductor TechnologyElectrical EngineeringElectronic DevicesDrain Biases	1995	145
Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond Qijiong Liu, A. Yagishita, N. Loubet, Low-power ElectronicsDevice ModelingElectrical EngineeringUtbb StructureEngineering	2010	79
Partially-depleted SOI technology for digital logic G. Shahidi, A. Ajmera, F. Assaderaghi, Hardware SecurityElectrical EngineeringSoi TechnologyEngineeringVlsi Design	2003	71
Channel doping impact on FinFETs for 22nm and beyond C.-H. Lin, R. Kambhampati, Robert J. Miller,	2012	66
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E. Leobandung, H. Nayakama, D. Mocuta, Electrical EngineeringEngineeringVlsi DesignAdvanced Packaging (Semiconductors)Nm Soi Technology	2005	65
Statistical measurement of random telegraph noise and its impact in scaled-down high-&#x03BA;/metal-gate MOSFETs Hiroshi Miki, Naoki Tega, Masanao Yamaoka, Hardware SecurityStatistical MeasurementElectrical EngineeringEngineeringVlsi Design	2012	62
A 0.063 &#x00B5;m<sup>2</sup> FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch V. Basker, T. Standaert, Hikaru Kawasaki, Novel Integration SchemeEngineeringVlsi DesignMicroscopyPattern Transfer	2010	60

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