N. Loubet - Concepedia

Author

N. Loubet

Also Known As

Loubet, N, Loubet, N., Loubet, Nicolas, Loubet, Nicolás A., N A Loubet, N. A. Loubet, N. Loubet, Nicolas LOUBET, Nicolas Loubet, Nicolás A. Loubet

Publications

1.2K

Citations

H-Index

Concepts

All Affiliations

STMicroelectronics (France)Laboratoire d'Électronique des Technologies de l'Information Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Institut polytechnique de Grenoble

About

N. Loubet is an author at STMicroelectronics (France) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	21	924
2	Applied Physics	14	18	735
3	Education	1	1	138
4	Natural Sciences	1	1	29
5	Chemistry	1	1	14

N. Loubet

Publications

1.1K

Citations

H-Index

Page 1

	Year	Citations
0.13 $\mu$m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications G. Avenier, Malick Diop, P. Chevalier, IEEE Journal of Solid-State Circuits EngineeringSige Bicmos TechnologyEducationMillimeter-wave ApplicationsIntegrated Circuits	2009	138
FDSOI devices with thin BOX and ground plane integration for 32nm node and below C. Fenouillet-Béranger, S. Denorme, P. Perreau, Solid-State Electronics 3D Ic ArchitectureElectrical EngineeringEngineeringVlsi DesignThin Box	2009	130
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond Qianlong Liu, M. Vinet, J. Gimbert, Semiconductor TechnologyElectrical EngineeringGate LengthEngineeringVlsi Design	2013	96
Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond Qijiong Liu, A. Yagishita, N. Loubet, Low-power ElectronicsDevice ModelingElectrical EngineeringUtbb StructureEngineering	2010	79
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K. Cheng, A. Khakifirooz, N. Loubet,	2012	74
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm<sup>2</sup> 6T-SRAM bitcell C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat, Pmos TransistorsSemiconductor TechnologyElectrical EngineeringEngineeringNanoelectronics	2007	61
High-k metal gate fundamental learning and multi-V<inf>t</inf> options for stacked nanosheet gate-all-around transistor Jingyun Zhang, Takashi Ando, Chun Wing Yeung, SemiconductorsSemiconductor TechnologyElectrical EngineeringEngineeringNanotechnology	2017	58
UTBB FDSOI transistors with dual STI for a multi-V<inf>t</inf> strategy at 20nm node and below L. Grenouillet, M. Vinet, J. Gimbert, Electrical EngineeringUtbb Fdsoi TransistorsEngineeringVlsi DesignVlsi Architecture	2012	53
FDSOI devices with thin BOX and ground plane integration for 32nm node and below C. Fenouillet-Béranger, S. Denorme, P. Perreau, EngineeringVlsi DesignThin BoxDevice IntegrationFdsoi Devices	2008	39
UTBB FDSOI scaling enablers for the 10nm node L. Grenouillet, Qinrang Liu, R. Wacquez, EngineeringVlsi DesignComputer ArchitectureElectromagnetic CompatibilityUtbb Fdsoi Technology	2013	29

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