P. Perreau

28nm FDSOI technology platform for high-speed low-voltage digital applications

N. Planes, O. Weber, V. Barral et al. · 2012 · 422 citations

Engineering, Vlsi Design, Emerging Memory Technology +16

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Sylvain Barraud, Matthieu Berthomé, R. Coquand et al. · IEEE Electron Device Letters · 2012 · 259 citations · Full text

Semiconductors, Semiconductor Technology, Electrical Engineering +15

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

C. Fenouillet-Béranger, S. Denorme, P. Perreau et al. · Solid-State Electronics · 2009 · 130 citations

3D Ic Architecture, Electrical Engineering, Engineering +12

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

F. Andrieu, O. Weber, J. Mazurier et al. · 2010 · 103 citations

Engineering, Vlsi Design, Integrated Circuits +16

14nm FDSOI technology for high speed and energy efficient applications

O. Weber, E. Josse, F. Andrieu et al. · 2014 · 89 citations

Low-power Electronics, Electrical Engineering, Engineering +9