F. Andrieu - Concepedia

Author

F. Andrieu

Commissariat à l'Énergie Atomique et aux Énergies Alternatives ORCID

Also Known As

A Boukenter, Andrieu, F., Andrieu, François, F. Andrieu, Francois ANDRIEU, Francois Andrieu, François Andrieu, P-046 Assylan

224

Publications

3.2K

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives Laboratoire d'Électronique des Technologies de l'Information CEA Grenoble Université Grenoble Alpes Institut polytechnique de Grenoble

About

F. Andrieu is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	26	71	2.6K
2	Applied Physics	25	63	2.5K
3	Social Sciences	2	2	28
4	Medicine	1	1	41
5	Natural Sciences	1	1	13

F. Andrieu

Publications

2.8K

Citations

H-Index

Page 1

	Year	Citations
Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance F. Mayer, C. Le Royer, J.-F. Damlencourt, Semiconductor TechnologyElectrical EngineeringEngineeringPhysicsApplied Physics	2008	237
High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding O. Weber, O. Faynot, F. Andrieu, Device ModelingSemiconductor TechnologyElectrical EngineeringEngineeringPhysics	2008	159
Advances, challenges and opportunities in 3D CMOS sequential integration P. Batude, M. Vinet, B. Prévitali, Materials Science3D Ic ArchitectureWafer Scale ProcessingEngineeringVlsi Design	2011	148
Performance and design considerations for gate-all-around stacked-NanoWires FETs Sylvain Barraud, V. Lapras, B. Prévitali, Electrical EngineeringGate-all-around Stacked-nanowires FetsEngineeringNanoelectronicsNanotechnology	2017	147
FDSOI devices with thin BOX and ground plane integration for 32nm node and below C. Fenouillet-Béranger, S. Denorme, P. Perreau, Solid-State Electronics 3D Ic ArchitectureElectrical EngineeringEngineeringVlsi DesignThin Box	2009	130
Engineering strained silicon on insulator wafers with the Smart CutTM technology B. Ghyselen, Jean‐Michel Hartmann, T. Ernst, Solid-State Electronics Insulator WafersSemiconductor TechnologyElectrical EngineeringEngineeringSilicon Debugging	2004	114
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F. Andrieu, O. Weber, J. Mazurier, EngineeringVlsi DesignIntegrated CircuitsUltra-thin BobyAdvanced Packaging (Semiconductors)	2010	103
Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node Marc Gaillardin, M. Martinez, Philippe Paillet, IEEE Transactions on Nuclear Science Tid BehaviorElectrical EngineeringTotal Ionizing DoseEngineeringIon Implantation	2013	75
Strained tunnel FETs with record I<inf>ON</inf>: first demonstration of ETSOI TFETs with SiGe channel and RSD A. Villalon, C. Le Royer, M. Cassé, Tunnelling ImprovementsSemiconductor TechnologyElectrical EngineeringSub XmlnsEngineering	2012	65
Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below C. Fenouillet-Béranger, P. Perreau, S. Denorme, Solid-State Electronics Electrical EngineeringSemiconductor DeviceEngineeringUltra-thin BoxAdvanced Packaging (Semiconductors)	2010	63

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