F. Andrieu

Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance

F. Mayer, C. Le Royer, J.-F. Damlencourt et al. · 2008 · 237 citations

Semiconductor Technology, Electrical Engineering, Engineering +12

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

O. Weber, O. Faynot, F. Andrieu et al. · 2008 · 159 citations

Device Modeling, Semiconductor Technology, Electrical Engineering +14

Advances, challenges and opportunities in 3D CMOS sequential integration

P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text

Materials Science, 3D Ic Architecture, Wafer Scale Processing +15

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Sylvain Barraud, V. Lapras, B. Prévitali et al. · 2017 · 147 citations · Full text

Electrical Engineering, Gate-all-around Stacked-nanowires Fets, Engineering +10

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

C. Fenouillet-Béranger, S. Denorme, P. Perreau et al. · Solid-State Electronics · 2009 · 130 citations

3D Ic Architecture, Electrical Engineering, Engineering +12