V. Lapras

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Sylvain Barraud, V. Lapras, B. Prévitali et al. · 2017 · 147 citations · Full text

Electrical Engineering, Gate-all-around Stacked-nanowires Fets, Engineering +10

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Sylvain Barraud, V. Lapras, Marie-Pierre Samson et al. · 2016 · 108 citations · Full text

Engineering, Inner Spacer, Integrated Circuits +16

Through silicon vias technology for CMOS image sensors packaging

David Henry, F. Jacquet, M. Neyret et al. · 2008 · 75 citations

Backside Technology, 3D Ic Architecture, Electrical Engineering +12

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

Sylvain Barraud, B. Prévitali, V. Lapras et al. · 2018 · 46 citations

Device Modeling, Gaa Fets, Electrical Engineering +13

Via first approach optimisation for Through Silicon Via applications

C. Laviron, B. Dunne, V. Lapras et al. · 2009 · 36 citations

Engineering, Vlsi Design, Computer Architecture +18