Marie-Pierre Samson - Concepedia

Author

Marie-Pierre Samson

Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Also Known As

M P Samson, M. P. Samson, M.-P. Samson, M.P. Samson, Marie-Pierre Samson, Samson, M. P., Samson, M.-P.

Publications

680

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives STMicroelectronics (France)Laboratoire d'Électronique des Technologies de l'Information CEA Grenoble Institut polytechnique de Grenoble

About

Marie-Pierre Samson is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in electrical engineering, engineering, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	13	603
2	Electrical Engineering	12	13	603
3	Applied Physics	11	12	584
4	Physics	2	2	37
5	Computer Engineering	1	1	19

Marie-Pierre Samson

Publications

622

Citations

H-Index

Page 1

	Year	Citations
Performance and design considerations for gate-all-around stacked-NanoWires FETs Sylvain Barraud, V. Lapras, B. Prévitali, Electrical EngineeringGate-all-around Stacked-nanowires FetsEngineeringNanoelectronicsNanotechnology	2017	147
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain Sylvain Barraud, V. Lapras, Marie-Pierre Samson, EngineeringInner SpacerIntegrated CircuitsSilicon On InsulatorSemiconductor Device	2016	108
Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width R. Coquand, M. Cassé, Sylvain Barraud, IEEE Transactions on Electron Devices SemiconductorsSemiconductor TechnologyElectrical EngineeringEngineeringSi Nanowire	2013	68
Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width R. Coquand, Sylvain Barraud, M. Cassé, Electrical EngineeringSi Film ThicknessEngineeringSemiconductor DeviceTechnology Scaling	2012	57
Highly performant double gate MOSFET realized with SON process S. Harrison, P. Coronel, F. Leverd, Electrical EngineeringEngineeringSon ProcessHigh Ion/ioff TradeNanoelectronics	2004	54
Thin-film devices for low power applications S. Monfray, C. Fenouillet-Béranger, G. Bidal, Solid-State Electronics Low-power ElectronicsElectrical EngineeringEngineeringThin-film FabricationMicrofabrication	2009	28
Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length P. Nguyen, Sylvain Barraud, C. Tabone, Semiconductor TechnologyCsige ChannelElectrical EngineeringSub XmlnsEngineering	2014	28
Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10nm width R. Coquand, Sylvain Barraud, M. Cassé, Solid-State Electronics Semiconductor TechnologyElectrical EngineeringNanoscale SystemEngineeringTechnology Scaling	2013	26
Strained Silicon Directly on Insulator N- and P-FET nanowire transistors Sylvain Barraud, Romain Laviéville, C. Tabone, SemiconductorsSemiconductor TechnologyElectrical EngineeringGate LengthEngineering	2014	20
Enhanced Performance of P-FET Omega-Gate SoI Nanowire With Recessed-SiGe Source-Drain Down to 13-nm Gate Length Sylvain Barraud, R. Coquand, Jean‐Michel Hartmann, IEEE Electron Device Letters EngineeringIntegrated CircuitsSilicon On InsulatorSemiconductor DeviceSemiconductor Nanostructures	2013	20

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