Publication | Closed Access
Highly performant double gate MOSFET realized with SON process
54
Citations
2
References
2004
Year
Unknown Venue
Electrical EngineeringEngineeringSon ProcessHigh Ion/ioff TradeNanoelectronicsElectronic EngineeringApplied PhysicsPower Semiconductor DevicePlanar ConfigurationDrive CurrentsMicroelectronicsOptoelectronicsSemiconductor Device
Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 /spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333 /spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained at 1.2 V with Tox = 20 /spl Aring/ and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.
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