F. Leverd

A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz f<inf>T</inf> / 370 GHz f<inf>MAX</inf> HBT and high-Q millimeter-wave passives

P. Chevalier, G. Avenier, G. Ribes et al. · 2014 · 171 citations

Low-power Electronics, Electrical Engineering, Millimeter Wave Technology +15

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

C. Fenouillet-Béranger, S. Denorme, P. Perreau et al. · Solid-State Electronics · 2009 · 130 citations

3D Ic Architecture, Electrical Engineering, Engineering +12

A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications

S. Crémer, Nathalie Vulliet, Thierry Pinguet et al. · 2013 · 94 citations

Photonics, Soi Wafers, Optical Interconnects +15

Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

C. Fenouillet-Béranger, P. Perreau, S. Denorme et al. · Solid-State Electronics · 2010 · 63 citations

Electrical Engineering, Semiconductor Device, Engineering +12

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell

C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat et al. · 2007 · 61 citations

Pmos Transistors, Semiconductor Technology, Electrical Engineering +13