Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Abstract

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> gain as high as +40% at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> = 45 nm is achieved for a multiple-NW active pattern.