T. Poiroux

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Sylvain Barraud, Matthieu Berthomé, R. Coquand et al. · IEEE Electron Device Letters · 2012 · 259 citations · Full text

Semiconductors, Semiconductor Technology, Electrical Engineering +15

Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Jean-Philippe Noël, Olivier Thomas, Marie-Anne Jaud et al. · IEEE Transactions on Electron Devices · 2011 · 183 citations

Semiconductors, Electrical Engineering, Engineering +15

Advances, challenges and opportunities in 3D CMOS sequential integration

P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text

Materials Science, 3D Ic Architecture, Wafer Scale Processing +15

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

Sylvain Barraud, R. Coquand, M. Cassé et al. · IEEE Electron Device Letters · 2012 · 145 citations

Electrical Engineering, Semiconductor Device, Engineering +11

Multiple gate devices: advantages and challenges

T. Poiroux, M. Vinet, O. Faynot et al. · Microelectronic Engineering · 2005 · 130 citations

Electrical Engineering, Engineering, Device Integration +4