M. Cassé - Concepedia

Author

M. Cassé

Commissariat à l'Énergie Atomique et aux Énergies Alternatives ORCID

Also Known As

André Juge, Casse, M., Casse, Mikael, Cassé, M., Cassé, Mikaël, M Casse, M Cassé, M. CASSE, M. Casse, M. Cassé

326

Publications

4.3K

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Laboratoire d'Électronique des Technologies de l'Information Institut polytechnique de Grenoble Université Grenoble Alpes

About

M. Cassé is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in electrical engineering, engineering, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	32	86	3.4K
2	Applied Physics	31	80	3.2K
3	Computer Engineering	15	24	966
4	Natural Sciences	3	3	163
5	Computer Science	1	1	134

M. Cassé

Publications

3.6K

Citations

H-Index

Page 1

	Year	Citations
Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm Sylvain Barraud, Matthieu Berthomé, R. Coquand, IEEE Electron Device Letters SemiconductorsSemiconductor TechnologyElectrical EngineeringSemiconductor DeviceEngineering	2012	259
Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm Sylvain Barraud, R. Coquand, M. Cassé, IEEE Electron Device Letters Electrical EngineeringSemiconductor DeviceEngineeringDiameter DownNanotechnology	2012	145
3DVLSI with CoolCube process: An alternative path to scaling P. Batude, C. Fenouillet-Béranger, L. Pasini, EngineeringVlsi DesignComputer ArchitectureComputer-aided DesignOptoelectronic Devices	2015	134
Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening Heorhii Bohuslavskyi, A. G. M. Jansen, Sylvain Barraud, IEEE Electron Device Letters	2019	134
Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters M. Cassé, L. Thévenod, B. Guillaumot, IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringPhysical InsightMetal GateEngineering	2006	131
FDSOI devices with thin BOX and ground plane integration for 32nm node and below C. Fenouillet-Béranger, S. Denorme, P. Perreau, Solid-State Electronics 3D Ic ArchitectureElectrical EngineeringEngineeringVlsi DesignThin Box	2009	130
Bonded planar double-metal-gate NMOS transistors down to 10 nm M. Vinet, T. Poiroux, J. Widiez, IEEE Electron Device Letters Alignment MarksElectrical EngineeringEngineeringNanoelectronicsScaling Rules	2005	128
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond O. Faynot, F. Andrieu, O. Weber, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsNon Planar Devices	2010	104
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F. Andrieu, O. Weber, J. Mazurier, EngineeringVlsi DesignIntegrated CircuitsUltra-thin BobyAdvanced Packaging (Semiconductors)	2010	103
7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing Sylvain Barraud, B. Prévitali, C. Vizioz, Semiconductor TechnologyElectrical EngineeringGaa TransistorsEngineeringNanoelectronics	2020	95

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