Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Abstract

In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) >; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . For the first time, an SS lower than 70 mV/dec is achieved at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.