IEEE Electron Device Letters · 2019 · 147 citations · 30 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSemiconductor MaterialsCmos Circuit DesignDevice CharacterizationDevice ModelingDevice ScalingMetal-oxide-semiconductor Field-effect TransistorsSemiconductor PhysicsDisorder-induced PropertiesFully Depleted Silicon-on-insulator TransistorsGate Oxide InterfacesGate Oxide Thickness EffectsInterface DensityInterface Trap DensitySaturationSubthreshold Swing
In the standard MOSFET description of the drain current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {I}_{{D}}$ </tex-math></inline-formula> as a function of applied gate voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {V}_{{ {GS}}}$ </tex-math></inline-formula> , the subthreshold swing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{SS(T)}}\equiv {{dV}}_{{{GS}}}/ {d}\log {I}_{ {D}}$ </tex-math></inline-formula> has a fundamental lower limit as a function of temperature <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}$ </tex-math></inline-formula> given by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${ {SS(T)}}=\ln 10\,\, {k}_{ {B}} {T}/ {e}$ </tex-math></inline-formula> . However, recent low-temperature studies of different advanced CMOS technologies have reported <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</i> (4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS(T)</i> in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi–Dirac statistics. This results in a subthreshold <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {I}_{ {D}}\sim {e}^{{{ {eV}}}_{{{GS}}}/ {k}_{ {B}} {T}_{0}}$ </tex-math></inline-formula> for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {T}_{0}=35$ </tex-math></inline-formula> K with saturation value <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${ {SS}}( {T}< {T}_{0})= \ln 10\,\, {k}_{ {B}} {T}_{0}/ {e}$ </tex-math></inline-formula> . The proposed model adequately describes the experimental data of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS(T)</i> from 300 down to 4 K using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {k}_{ {B}} {T}_{0} \simeq 3$ </tex-math></inline-formula> meV for the width of the exponential tail and can also accurately describe <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${ {SS}}( {I}_{ {D}})$ </tex-math></inline-formula> within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.
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Engineering, Computer Engineering, Electrical Engineering +17