Advances, challenges and opportunities in 3D CMOS sequential integration

TLDR

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. The paper addresses the major challenges of 3D sequential integration, focusing on controlling molecular bonding to achieve pristine top active layers. The authors use Solid Phase Epitaxy at 600 °C to match top FET performance with bottom devices. A stable salicide preserves bottom device performance after top FET processing, enabling a wide range of applications.

Abstract

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.